A Novel Design of Efficient Multi-channel UART Controller Based on FPGA

In traditional universal asynchronous receiver transmitter (UART) controller, the data transmission is inefficient and the data bus utilization ratio is low. A novel design is provided to solve these problems. The architecture of the system is introduced, the flow charts of data processing as well as the implementation state machine are also presented in detail. This paper is concluded by comparing the performance of this design, which is realized on field programmable gate array (FPGA) using Verilog hardware description language (HDL), with other traditional UART controllers.

作 者： HU Zhe ZHANG Jun LUO Xi-ling   作者單位： Department of Electronic Information Engineering Beijing University of Aeronautics and Astronautics, Beijing 100083, China  刊 名： 中國航空學(xué)報（英文版）  ISTIC 英文刊名： CHINESE JOURNAL OF AERONAUTICS  年，卷(期)： 2007 20(1)  分類號： V2  關(guān)鍵詞： serial communication   UART   multi-channel   FPGA  

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